SE organises a talk by Dr. Vivek Singh

Event From Date: 
Thursday, 28 March 2019
Event End Date: 
Thursday, 28 March 2019
Event Title: 
SE organises a talk by Dr. Vivek Singh
Event Details: 
School of Engineering
organising a talk by
 
Dr. Vivek Singh
Intel Corporation
 
on
 
Computational Imaging: Scaling Walls
 
on March 28, 2019 @ 11:30am
Seminar Room, School of Engineering, JNU
 
 
ABSTRACT
 
Moore’s Law is an observation that a transistor – the fundamental building block of the digital age – will decrease in cost at a steady, exponential rate. This decrease in cost as well as transistor size over the past 50 years has also led to dramatic increases in compute power and energy efficiency and transformed our world with ever-more powerful smart phones, tablets, personal computers and data centers. It has also enabled computing to become a powerful yet invisible force in our homes, offices, cars, factories and much more. While industry observers continue to predict that Moore’s law will hit the wall, motivated teams continue to find innovative solutions to scale the wall. Many of the challenges and innovations that enable Moore’s Law scaling are in the field of imaging and mask manufacturing. This talk will describe some of those challenges and associated opportunities, with a particular focus on three facets of Computational Imaging: Inverse Lithography, Computing for EUV (Extreme Ultraviolet), smart metrology, and AI. Inverse lithography enables better utilization of the resolution capability of a lithography tools and masks. Computing for EUV ensures that EUV is a leading option for next generation lithography to further enhance scaling and design rule flexibility. Smart metrology and AI enable better identification of defects from metrology tools which is critical for high volume manufacturing. Such innovations, fed by a rich technology pipeline, give us confidence that Moore's Law will continue.
 
 
Brief Bio-Sketch : Vivek Singh is an Intel Fellow and Director in Intel’s Technology and Manufacturing Group, and  manages the Computational Imaging Department.  He is responsible for all of Intel’s tool development in full-chip OPC, lithography verification, modeling, next-generation lithography selection, inverse lithography technologies, double patterning, image processing, smart metrology and AI for yield, and design rule creation. He is an SPIE Fellow, and the current President of the Lithography Workshop. He holds 44 patents, has published more than 50 technical papers, and he and his team have won 5 Intel Achievement Awards. Singh graduated from the Indian Institute of Technology, Delhi with a bachelor's degree in chemical engineering in 1989. He earned a master's degree in chemical engineering in 1990, a Ph.D. minor in electrical engineering in 1993, and a Ph.D. in chemical engineering in 1993, all from Stanford University.